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Conference Publications

Rohit Sharma and C.P. Ravikumar. Design issues in synthesis of reusable cores. To be presented at the Great Lakes VLSI Symposium, Michigan, Ann Arbor, 1999.

A Shyamprakash, Ram G. Mohan, C.P. Ravikumar. Parametrized Divided Cells for Synergy SmartBlocks. Proceedings of the Cadence Technical Conference, 1998. Pages 469-471.

C.P. Ravikumar and N. Agrawal. Adaptive Routing in Multicomputers: A Tutorial. Presented at Workshop on High Performance Computing, Indian Statistical Institute, January 1999.

C.P. Ravikumar, A.Mittal. Efficient Delay Fault Simulator for Modular Circuits. Proceedings of the Twelfth International Conference on VLSI Design (IEEE). Goa, India. January 1999.

C.P. Ravikumar, R.K. Patney, M. Sharma. Improving the diagnosability of digital circuits. Proceedings of the Twelfth International Conference on VLSI Design (IEEE). Goa, India. January 1999.

C.P. Ravikumar and N. Satya Prasad. Evaluating BIST Architectures for Low Power. Proceedings of the Seventh Asia Test Symposium (ATS '98, IEEE), Singapore, Pages 430-434.

C.P. Ravikumar, D.R. Pandit, A.Mishra. Performance-driven Design and Redesign of High-speed Local Area Networks. Proceedings of the fifth International Conference on High Performance Computing (HiPC'98, IEEE). Chennai, India. December 1998. Pages 416-421.

Girish Kumar, Nishit Narang, C.P. Ravikumar. Efficient Algorithms for Delay-bounded minimum-cost path problem in Communication Networks. Proceedings of the fifth International Conference on High Performance Computing (HiPC'98, IEEE). Chennai, India. December 1998. Pages 141-146.

C.P.Ravikumar, Ram G.Mohan & S.Patel.  Delay constrained power minimisation through technology mapping and placement.  Proceedings on emerging microelectronics & interconnection technology. (EMIT'98). Pages 261--267.

V.Sahula, C.P.Ravikumar & D.Nagchoudhari. Optimal interconnect modelling and synthesis.  Proceedings on emerging microelectronics & interconnection technology.(EMIT'98).

C.P.Ravikumar J.Minocha & R.Aggarwal. MCM Partitioning for lower power applications. Proceedings on emerging microelectronics & interconnection technology.(EMIT'98).

S.A.Wadekar, A.C.Parker & C.P.Ravikumar. FREEDOM: Statistical behaviour estimation of system energy and power. Proc. of the 11th International conference on VLSI Design. Jan. 1998, PP.30-36.

C.P.Ravikumar,Sumit Gupta & Akshay Jajoo. Synthesis of testable RTL designs. Proceedings of the 11th International conference on VLSI Design. Jan. 1998, PP.187-192.

M.F.Abdulla, C.P.Ravikumar & Anshul Kumar.  Hybrid testing schemes based on mutual and signature testing. Proc. of the 11th International conference on VLSI Design. Jan. 1998, PP.293-296.

Dong-Hyun Heo & A.C.Parker,C.P.Ravikumar.  An evolutionary approach to system redesign. Proceedings of the 11th International conference on VLSI Design. Jan. 1998, PP.359-362.

M.F.Abdulla, C.P.Ravikumar & Anshul Kumar. On-chip signature checking for embedded memories. Proceedings of the 11th International conference on VLSI Design. Jan. 1998, PP.558-563.

Ramnik Bajaj, C.P.Ravikumar & Suresh Chandra.  Distributed delay constrained multicast path setup algorithm for high speed networks. Proceedings on Fourth international conference on High Performance computing. Dec.1997, PP.438-442

M.F. Abdulla, C.P. Ravikumar, Anshul Kumar. A Scheme for Multiple On-chip Signature Checking for Embedded SRAMs, Proceedings of European Design and Test Conference, Paris, France, March 1997.

C.P. Ravikumar, A.R. Thomas and A. Gupta. A Genetic Algorithm for Assembling Optical Computers Using Faulty Optical Arrays, International Conference on High-Performance Computing, December 1996, India.

S. Habib, C.P. Ravikumar and A.C. Parker.  Storage Allocation and Scheduling Problems in Web Caching Applications.  International Workshop on Web Caching, organized by NLANR, USA.  Colorado, Boulder.  USA. 1997.

Dong-Hyun Heo & A.C.Parker, C.P.Ravikumar. Rapid synthesis of multichip systems.  Proceedings of the 10th International conference on VLSI Design. Jan. 1997, PP.62-68.

C.P.Ravikumar & R.Aggarwal. A graph-theoretic approach for register file based synthesis.  Proceedings of the 10th International conference on VLSI Design. Jan. 1997, PP.118-123.

M.F.Abdulla, C.P.Ravikumar & Anshul Kumar. Efficient implementation of multiple on-chip signature checking. Proceedings of the 10th International conference on VLSI Design. Jan. 1997, PP.297-302.

C.P.Ravikumar,Vikas jain & Anurag Dod. Faster fault simulation through distributed computing. Proceedings of the 10th International conference on VLSI Design. Jan. 1997, PP.482-487.

M.F. Abdulla, C.P. Ravikumar, Anshul Kumar. BIST With Multiple On-chip Signature Comparisons. IEEE European Design and Test Workshop, Montpellier, France, pages 27-31, June 1996.

M.F. Abdulla, C.P. Ravikumar, Anshul Kumar. A novel architecture with built-in self-check. Proceedings of the 9th ACM/IEEE Inernational Conference on VLSI Design, Bangalore, India, Pages 57-60, January 1996.

D.R.Pandit & C.P.Ravikumar. Call admission control and routing in ATM networks for multimedia communications. Proceedings of the international conference on multimedia,Jan 1998, PP.94-102

Anubhav Mishra & C.P.Ravikumar. Design and performance analysis of a cellular network with support for multicasting.  Proc. of the international conference on Multimedia, Jan 1998, PP.103-113.

Dong-Hyun Heo & A.C.Parker,C.P.Ravikumar. Synthesis of optimal MCM-based systems. EEP-vol. 19-1, Advances in electronic packaging-1997,Vol. 1, ACME 1997,PP.843-850

N.Agrawal & C.P.Ravikumar. An Euler-tour based technique for deadlock-free multicasting. Proc. of international conference on parallel processing. August 1997,Chicago,IL. Pages 378--384.

C.P.Ravikumar & V.Arora. Deadlock-free multicasting in multicomputers based on Two-path Cover. Proc.of ADCOMP'97, Chennai, INDIA,1997. Pages 493--500.

C.P.Ravikumar & C.P.Gupta. Parallel algorithm for branch-and-bound. Proceedings of international conference on parallel processing. August 1997,Chicago,IL.  Pages 431--438.

C.P.Ravikumar, Dilip Raj Pandit,Anubhav Mishra & Abhinav Mathur. Topological design of Local Area Networks. Southeast asia region conference on communications,New Delhi 1997.

D.-H. Heo, C.P. Ravikumar and A.C. Parker.  A Synthesis tool targeted for Rapid Delivery of Electronic Systems.  International Workshop on Electronic Design Processes (IEEE), Santa Clara, April 1996.

C.P. Ravikumar, N. Agrawal and P. Agarwal.  Efficient Delay Test Generation for Module-level Circuits.  In Proceedings of the Great Lakes VLSI Symposium (IEEE), 1996.

C.P. Ravikumar, S. Ahmad and V. Agrawal.  Path Cover Problem for General Graphs with applications to Deadlock-free routing in multicomputers.  Computer Society of India's Annual Convention, Bangalore, India, October 1996.

N. Sharma and C.P. Ravikumar.  Improving the confidence of IDDQ testing through Testability-driven Layout.  International Symposium on IDDQ Testing, 1996.

N. Agrawal and C.P. Ravikumar. Adaptive Multicasting in Massively Parallel Computers. December, 1996. Proceedings of the International Conference on Advanced Computing.

R. Parthiban, C.P. Ravikumar, R. Kakarala, and J. Sivaswamy.  Parallel algorithms for symmetry detection. In Proc. of Int. Conference on High Performance Computing, pages 569--573, 1995.

N. Agrawal and C.P. Ravikumar.  Hierarchical Routing Algorithm for Multiply Twisted Hypercubes. In Proceedings of Parallel and Real-time Systems Conference   (PART), Australia, 1995.

A. Shyamprakash and C.P. Ravikumar. Verilog Modeling and Simulation of a Communication Coprocessor for  Multicomputers. In Open Verilog Interface Conference, Santa Barbara (IEEE), 1995.

C.P. Ravikumar, V.Jain, and G.S. Thandi. Simulated Annealing for Technology Mapping in FPGAs.  In Proceedings of National Systems Conference, Agra, India, pages 400--405, January 1995.

C.P. Ravikumar and H.Joshi. HISCOAP -- A Hierarchical Testability Analysis Tool. In Proc. of the International Conference of VLSI Design  (IEEE), New Delhi, India, pages 272--277, January 1995.

C.P. Ravikumar and R.Aggarwal. A Parallel Search-and-Learn Algorithm for Graph Coloring. In Proceedings of the International Workshop on Parallel Processing, Bangalore, India}, pages 61--66, December 1994.

C.P. Ravikumar and G.Manimaran. An ATM Switch Fabric Based on Indirect Star Graphs. In Symposium on Parallel and Distributed Processing (IEEE), Dallas, 1994.

C.P. Raviumar and A.Shyamprakash. VLSI Implementation of a Wormhole Router using Virtual Channels. In Proceedings of the IEEE Tencon, Singapore, pages 1035--1039, 1994.

C.P. Ravikumar and A.M. Goel. Deadlock Free Routing Algorithms for Star Graphs. In Proceedings of the National Symposium on Theoretical Computer Science, Kanpur, India, June 1994.

C.P. Ravikumar and H. Rasheed. Simulated Annealing for Target-Oriented Partial Scan.  In the Proceedings of the International Conference on VLSI Design (IEEE), Calcutta, India, January 1994. pp. 107 -- 112.

C.P. Ravikumar and A. Kuchlous.  Two-way Partitioning of Shuffle-Exchange and DeBruijn Graphs.  In the Proceedings of the National Symposium on Theoretical Computer Science, Kharagpur, India.  June 1993. pp. 1--10.

C.P. Ravikumar, A. Kuchlous, and G. Manimaran.  Incomplete Star Graph -- An Economical, Fault-tolerant Interconnection Network.  In the Proceedings of the International Conference on Parallel Processing, St. Charles, Illinois, USA. August, 1993. pp. I-83 -- I-90.

C.P. Ravikumar. Parallel Search-and-Learn Technique for Solving Large Scale TSP. In the Proceedings of the International Conference on Tools with Artificial Intelligence (IEEE), Boston, USA. 1993. pp. 381 -- 388.

C.P. Ravikumar and R.K. Gandhi. Parallel Neural Algorithm for Solving Large Scale TSP.  In the Proceedings of the National Systems Conference, Kanpur, India, December 1993. pp. 122--126.

C.P. Ravikumar, R.K. Gandhi and L.M. Patnaik. Parallel Neural Algorithm for TSP Based on Divide-and-Conquer, ANZIIS Conference (IEEE), December 1993, Australia.

C.P. Ravikumar and R. Sethi.  SHARP -- A Parallel Shape Recognition Algorithm.  In the Proceedings of the Indo-US Workshop on Parallel Algorithms for Digital Signal Processing, Pune (India), 1993.