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Last updated on Oct 14, 2016

 

To know the citation information for these papers, please visit http://scholar.google.com/ and type the title of the paper. All IEEE publications are available through IEEE Explore.

 

Journal Publications of C.P. Ravikumar

 

56. C.P. Ravikumar. Smart and Fault-Tolerant LED-Based Street Lamps. Journal of Low Power Electronics, 12, 259-266 (2016).

55.N. Sharma, V. Sahula and C.P. Ravikumar. Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation. IJASCSE, VOL 1, ISSUE 4, 2012.

 

54. T.S. Rajesh Kumar, R. Govindarajan, C.P. Ravikumar. On-Chip Memory Architecture Exploration Framework for DSP Based Embedded System on Chip. ACM Transactions on Embedded Computing Systems. , Vol. 11, No. 1, Article 5, Publication date: March 2012.

 

53. C.P. Ravikumar, M. Hirech and X. Wen. Test Strategies for Low Power Devices. Journal of Low Power Electronics, American Scientific Publishers (2008).

 

  1. V. R. Devanathan, C. P. Ravikumar, Rajat Merhotra and V. Kamakoti. A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. Journal of Low Power Electronics, American Scientific Publishers, 4, 101110 (April, 2008).

 

51.  V.R. Devanathan, C.P. Ravikumar, V. Kamakoti, Variation-Tolerant, Power-Safe Pattern Generation. IEEE Design and Test. Volume: 24, Issue 4. Page(s): 374-384. April 2007.

50.  T. Senthil Arasu, C. P. Ravikumar, and S. K. Nandy, Low-Power Hierarchical Scan Test for Multiple Clock Domains. JOLPE ASP Journal of Low Power Electronics, Vol. 2, No 3, Pages 1-13, 2007.

49.  V.R. Devanathan, C.P. Ravikumar, and V. Kamakoti. On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. JOLPE - ASP Journal of Low Power Electronics, Vol. 2 N3, December 2006. Pages 464-476. American Scientific Publishers.

48.  N. Ahmed, M. Tehranipoor, C.P. Ravikumar and K. Butler, Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), vol. 26, no. 5, pp. 896-906, May 2007.

47.  M. ElShoukry and M. Tehranipoor and C.P. Ravikumar, A Critical-Path Aware Partial Gating Approach for Test Power Reduction, ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12 ,  Issue 2, April 2007.

46.  C.P. Ravikumar. Multiprocessor Architectures for Embedded Video Streaming Applications. Computer Society of India Communications. January 2006. Pages 19-25.

45.  C.P. Ravikumar, V. Visvanathan, and Vinod Menezes. Challenges in Implementation of VLSI Architectures. Computer Society of India Communications. January 2006. Pages 15-18.

44.  C.P. Ravikumar. Guest Editorial Processor Architectures. Computer Society of India Communications. January 2006. Pages 4-5.

43.  M.F. Abdulla and C.P. Ravikumar. A Self-Checking Signature Scheme for Checking Backdoor Security Attacks in Internet. Journal of High Speed Networks, IOS Press, 2004., Pages 309-318.

42.  S.H. Srinivasan and C.P. Ravikumar. Guest Editorial Storage Area Networks. Computer Science and Informatics - The Journal of the Computer Society of India. Special Issue on Storage Area Networks. Vol. 33, No. 4, October-Dec, 2003.

41.     C.P. Ravikumar and A. Dod and V. Jain. Distributed Fault Simulation on Parallel Virtual Machine. International Journal of VLSI DESIGN. 2001, Vol. 12, No. l, pp. 81 99.

40.  C. P. Ravikumar, S. Chakraverty and D. Roy Chowdhury. Synthesis of Performance Critical Heterogeneous Computing Systems Using Genetic Algorithm under a Stochastic Framework. IETE Technical Review. Special Issue on Genetic Algorithms. 2002.

39.  C. P. Ravikumar, Mita Sharma and Prachi Jain. Optimal Design of Delay Bounded WDM Networks Using a Genetic Algorithm. IETE Technical Review. Special Issue on Genetic Algorithms. 2002.

38.  C.P. Ravikumar, Manish Sharma, and R.K. Patney. Improving the Diagnosability of Combinational Circuits through Test point Insertion. Accepted for publication in the Journal of System Architecture, 2000.

37.  C.P. Ravikumar. On Writing a Thesis. IETE Journal of Education. Invited Article, 2000. Pages 45-52.

36.  M.M.S. Beg and C.P. Ravikumar. Parallel and Distributed Algorithms for e-commerce applications. Special issue on e-commerce, IETE Technical Review, Vol. 17, no. 4, July-August, 2000, pp. 189-195.

35. C.P. Ravikumar and R. Aggarwal. Graph Algorithms for Multiport Memory based Synthesis. Accepted for publication in IEEE Transactions on VLSI Systems. Editor D. Bouldin. 1999.

34. M.F. Abdulla, C.P. Ravikumar, and Anshul Kumar. A Scheme for Multiple On-chip Signature Checking for Embedded SRAMs. Journal of System Architecture, 46 (2000), 181-199

33. M.F. Abdulla, C.P. Ravikumar and Anshul Kumar. Built-in Self Test based on Multiple On-chip Signature Checking. Journal of Electronic Testing: Theory and Applications, Kluwer Publishers, 1999, 227-244.

32. C.P. Ravikumar, G.S. Saund, N. Agrawal. A functional-level testability measure for register-level circuits and its estimation. Microprocessors and Microsystems. Vol 22, 1999. Pages 535--542.

31. C.P. Ravikumar and S. Chakraverty.  VLSI Implementation of a Strongly Fault-Secure ALU.  International Journal of Computer Systems Science and Engineering, Vol 13, No 5, September 1998, Pages 125-131.

30. C.P. Ravikumar. Software Development and Kannada Language. In Aniketana, a journal of Kannada Language and Literature published by the Karnataka Sahitya Akademy, July-Sept 1998. Pages 25-33.

29. M.F. Abdulla, C.P. Ravikumar and Anshul Kumar. Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. Journal of Electronic Testing: Theory and Applications, 12, 199-216, and 1998. Kluwer Academic Publishers.

28. C.P. Ravikumar and H. Joshi.  SCOAP-based Testability Measure for Hierarchical Circuits.  International Journal of VLSI Design. 1998. Vol. 7, No. 2, Pages 131-141.

27. C.P. Ravikumar and N. Sharma.  Testability-driven layout of Combinational Circuits. International Journal of VLSI Design, 1998. Vol. 7, No. 4, 347-352.

26. C.P. Ravikumar and R. Bajpai. Source-based Delay-bounded multicasting based on Genetic Algorithms.  Computer Communications, Vol 21, Pages 126-132, 1998.

25. C.P. Ravikumar, T. Rai, and V. Verma.  Kautz Graphs as Attractive Logical Topologies in WDM Networks.  Computer Communications, 20, Pages 1259-1270, 1997.

24. C.P. Ravikumar, N. Agrawal, and P. Agarwal.  Hierarchical Delay Test Generation. Journal of Electronic Testing, Kluwer Academic Publishers, 1997. Pages 231--244.

23. C.P. Ravikumar and R.K. Gandhi.  A Parallel Neural Algorithm for Large Scale TSP. Special Issue on Neural Networks, Computer Science and Informatics, Computer Society of India, 1997. Vol. 27, No. 1, 2-10.

22. C.P. Ravikumar and C.S. Panda. Adaptive Routing on k-ary n-cubes using Incomplete Diagnostic Information.  Microprocessors and Microsystems,  Vol 20, 1997.  Pages 351-360.

21. R. Parthiban, C.P. Ravikumar, J. Sivaswamy and R. Kakarala.  Parallelization of Symmetry Detection Algorithms on a Network of Workstations.  Microprocessors and Microsystems, 20, Pages 341-349, 1997.

20. N. Agrawal and C.P. Ravikumar.  Fault-tolerant Routing in Multiply Twisted Cube Topology.  Journal of Systems Architecture, 42, Pages 279-288, 1996.

19. C.P.Ravikumar and V. Saxena. TOGAPS -- A Testability Oriented Genetic Algorithm for Pipeline Synthesis. International Journal of VLSI Design, Gordon and Breach Publishers,  5(1), 1996. Pages 77-88.

18. C.P. Ravikumar and R. Aggarwal.  Parallel Search-and-Learn Algorithm and Graph Coloring.  Knowledge Based Systems. Volume 9.  Pages 3--13, 1996.

17. C.P. Ravikumar and A.Kuchlous.  Two-way Partitioning of Shuffle-Exchange and DeBruijn Graphs. International Journal of Computer Systems -- Science and Engineering, Butterworth Publishers, 1995.

16. C.P. Ravikumar and A.K. Gupta. A Genetic Algorithm for Mapping Tasks to a Reconfigurable Parallel Processor. IEE Proceedings--E, 142:81--86, March 1995.

15. C.P. Ravikumar and R.Sethi. SHARP: A Parallel Shape Recognition Algorithm. The Journal of Microprocessors and Microsystems, Butterworth-Heinemann, 19(3):131--138, April 1995.

14. C.P. Ravikumar and A.M. Goel. Deadlock-free Wormhole Routing Algorithms for Star Graph Topology. IEE Proceedings, Comput. Digit. Tech., Vol. 142, No. 6, Pages 395-400, November 1995.

13. C.P. Ravikumar and N.Vedi.  Heuristic and Neural Algorithms for Mapping Tasks to Reconfigurable Parallel Processors. Elsevier Science Publishers. Journal of Microprocessors and Microprogramming, 41(2):137--151, May 1995.

12. N. Agrawal and C.P. Ravikumar. Adaptive wormhole routing for high-reliability in massively parallel processors. IETE Technical Review. May 1995, Vol. 12, No. 3, Pages 191-203.

11. C.P. Ravikumar.  Parallel Search-and-Learn Technique for Solving Large-Scale TSP.  International Journal of Knowledge Based Systems, Butterworth-Heinemann, 7(3): 169--176, September 1994.

10. C.P. Ravikumar and H. Rasheed.  Simulated Annealing for Partial Scan Design. Arabian Journal of Science and Engineering, 19(48): 845--855, October 1994.

9. C.P. Ravikumar and H. Rasheed.  TOPS -- A Target-Oriented Partial Scan Design Package. International Journal of VLSI Design, Gordon and Breach Publishers, USA, pages 233--239, 1994.

8. C.P. Ravikumar and S. Sastry, "LARA : A Layout Accelerator Based on Reduced Array Architecture," in CAD Accelerators (A. P. Ambler, P. Agrawal, and W. R. Moore, eds.), Elsevier Science, 1991.

7. C.P. Ravikumar and S. Sastry. A Parallel Approach to Three Layer Channel Routing. In CAD Accelerators (A. P. Ambler, P. Agrawal, and W. R. Moore, eds.), Elsevier Science, 1991.

6. C.P Ravikumar and S. Sastry, "VYUHA: A Detailed Router for Multiple RoutingModels," INTEGRATION: The VLSI Journal, no. 11, pp. 141- 157, 1991.

5. C.P. Ravikumar, S. Sastry, and L.M. Patnaik. , "Parallel Min-Cut Placement on Reduced Hardware SIMD Architecture," Journal of Computer Systems Science and Engineering, vol. 6, no. 1, pp. 3-11, 1991

4. C.P. Ravikumar and S. Sastry, "Placement Accelerators," in Progress in Computer Aided VLSI Design (G. W. Zobrist, ed.), vol. 5, Ablex Publishers, 1990.

3. C.P. Ravikumar and S. Sastry. "A Hardware Accelerator for Hierarchical VLSI Routing," Integration: The VLSI Journal, no. 7, pp. 283-302, 1989

2. C.P. Ravikumar S. Sastry, "Parallel Placement on Hypercube Architecture," Int'l Journal of Computer Aided VLSI Design, vol. 2, pp. 159- 179, 1990.

1. C.P. Ravikumar, S. Sastry, and L. Patnaik, "Parallel Circuit Partitioning on a Reduced Array Architecture," Computer Aided Design, vol. 21, no. 7, pp. 447-455, 1989.