Updated on October 1, 2007

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Conference Publications of C.P. Ravikumar

 

  1. A. Kokrady, C.P. Ravikumar, Nitin Chandrachoodan. Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs. Asian Test Symposium, 2008. (Sapporo, Japan).
  2. C.P. Ravikumar, M. Hirech and X. Wen. Test Challenges for Low-Power Devices. Proceedings of the IEEE Conference on Design Automation and Test in Europe, DATE 2008, Munich, Germany.
  3. A. Kokrady, C.P. Ravikumar, and N. Chandrachoodan. Memory Yield Improvement through Multiple Test Sequences and Application aware Fault Models. International Conference on VLSI Design, Hyderabad, 2008.
  4. T.S. Rajesh Kumar, C.P. Ravikumar, and R. Govindarajan. Memory Architecture Exploration Framework for Cache Based Embedded SoC. International Conference on VLSI Design, Hyderabad, 2008.
  5. C.P. Ravikumar. Power and Power-Infrastructure Aware Test Pattern Generation. Invited Talk, 5th IEEE East West Design and Test Symposium, Armenia, 2007.
  6. V.R. Devanathan, CP. Ravikumar, V. Kamakoti. A Stochastic Pattern Generation and Optimization Framework for Variation-tolerant, Power-safe Scan Test. International Test Conference, Santa Clara, October 2007.
  7. V.R. Devanathan, CP. Ravikumar, R. Mehrotra, V. Kamakoti. PMScan : A Power-managed Scan for Simultaneous Reduction of Dynamic and Leakage Power During Scan Test. International Test Conference, Santa Clara, October 2007.
  8. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS 2007, Berkeley, CA. 167-172.
  9. C.P. Ravikumar, M. Hussain and S. Krishnamurthi. Collaborative and Innovative DFT for "Pushing-the-envelope" Designs. SNUG 2007. Bangalore.
  10. T.S. Rajesh Kumar, C.P. Ravikumar, and R. Govindarajan. MODLEX: Multi Objective Data Layout Exploration for Embedded Systems on Chip.  ASPDAC 2007, Japan.
  11. T.S. Rajesh Kumar, C.P. Ravikumar, and R. Govindarajan. MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. International Conference on VLSI Design/Embedded System Design, 2007. 527-533.
  12. V.R. Devanathan, C.P. Ravikumar, and V. Kamakoti. On Reducing Transition Fault Test Time and Test Power for SoCs in Hierarchical Scan Test. International Design and Test Workshop, Dubai, November 2006.
  13. Jais Abraham, Sandeep Jain, CP Ravikumar - Texas Instruments Pvt Ltd, David Buyze, Edwin Silveira, Sumitha Krishnamurthy - Synopsys, Inc. Simpler Diagnosis of Deterministic BIST. SNUG 2006, Bangalore, 2006.
  14. V.R. Devanathan, C.P. Ravikumar, V. Kamakoti. Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms”. International Conference on VLSI Design/Embedded System Design, 2007.  Bangalore. 351-356

15.  M. ElShoukry, C.P. Ravikumar and M. Tehranipoor. Partial Gating Optimization for Power Reduction During Test Application. Asian Test Symposium, Kolkata, India, December 2005.

16.  C.P. Ravikumar, Aman Kokrady, Rajat Mehrotra. BIST Issues in Embedded Memories with Bus Encoding. IEEE TTTC Technical Forum in honor of Prof. S.M. Reddy. Austin, Texas, November 2005.

17.  C.P. Ravikumar and T.S. Rajesh Kumar. Multiprocessor Architectures for Embedded Video Streaming Applications. IEE Embedded Systems and Software Conference, November 2005, Bangalore.

18.  Senthil Arasu, C.P. Ravikumar, and S.K. Nandy.  “A Low Power and Low Cost Scan Test Architecture for Multi-clock Domain SoCs using Virtual Divide-and-Conquer .” IEEE International Test Conference, 2005, November, 2005.

19.  N. Ahmed, M. Tehranipoor, C.P. Ravikumar and J. Plusquellic, “At-Speed Transition Fault Testing Using Low Speed Testers With Application to Reduced Scan Enable Routing Area,” IEEE North Atlantic Test Workshop (NATW'05), 2005.

20.  N. Ahmed, C.P. Ravikumar, M. Tehranipoor and J. Plusquellic, “At-Speed Transition Fault Testing With Low Speed Scan Enable,” IEEE VLSI Test Symposium (VTS'05), pp. , 2005. (Won the best paper award.)

  1. C.P. Ravikumar, N. Ahmed and M. Tehranipoor, “Practicing Transition-Fault Testing with Physical-Design-Friendly Flows,” Texas Instruments India Technical Conference (TIITC’05), 2005. (Ranked 5th Among 89 Presentations).
  2. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, “Enhanced Launch-off-Capture Transition Fault Testing,” to appear in IEEE International Test Conf. (ITC'05), 2005 (Ranked in top ten among 134 papers).

3.      C.P. Ravikumar, R. Dandamudi, V.R. Devanathan, N. Haldar, K. Kiran, P.S. Vijay Kumar. A Framework for Distributed Design-for-Test”, International Conference on VLSI Design 2005.

  1. C.P. Ravikumar. “DFT Productivity Enhancement through the CC-DFTM Integrated DFT Flow – Case Study of Deployment on OHIO DSL CHIP,” TI Technical Conference, 2004.
  2. T.S. Rajesh Kumar, C.P. Ravikumar, R. Govindarajan. HEURISTIC AND EVOLUTIONARY APPROACH TO DATA LAYOUT PROBLEM IN EMBEDDED SYSTEMS, TI India Technical Conference, 2004.  (Winner of the honorable mention award in the technical paper category.)

6.      C.P. Ravikumar and G. Hetherington. A Holistic Parallel and Hierarchical Approach towards Design-for-Test. International Test Conference, 2004.

7.      M.F. Abdulla and C.P. Ravikumar. A self-checking signature scheme for checking backdoor security attacks in Internet. National Conference on Communications, Bangalore, 2004.

8.      M.F. Abdulla and C.P. Ravikumar. Trojan Detection Using Time Fingerprints In A Self Checking Signature Scheme. HiPC Workshop on Trusted Internet, High Performance Computing Conference, Hyderabad, 2003.

9.      C.P. Ravikumar. Multiprocessor Architectures for Embedded Video Streaming Applications. HiPC Workshop on Embedded Systems for Video Streaming, 2003.

10.  A. Kokrady, C.P. Ravikumar. Fast, Layout-aware validation of test-vectors for nanometer-related timing failures. Proceedings of the 17th International Conference on VLSI Design, Mumbai, 2004.

11.  C.P. Ravikumar. Multiprocessor Architectures for Embedded Systems. Proceedings of the 17th International Conference on VLSI Design, Mumbai, 2004.

12.  C.P. Ravikumar Rajat Mehrotra, S. Phani Kumar. Estimation of Memory Test Power. TI India Technical Conference, 2003. 

13.  C.P. Ravikumar, Graham Hetherington, Rajanikanth D., Raghuraman R., Nirmalya Haldar, S. Arasu, Charu Srimali. A Stitched flow for Design-for-Testability. TI India Technical Conference, 2003.

14.  A Kokrady and C.P. Ravikumar. Static Verification of Test Vectors for IR Drop Failure. ICCAD 2003. 

15.  A. Kokrady, R. Mehrotra, C.P. Ravikumar and S. Phanikumar. Estimating Test Power Dissipation for Embedded Memories. VDAT 2003.

16.  C.P. Ravikumar and Nitin Kakkar. Mutual Testing based on Wavelet Transforms. Accepted for presentation at VLSI Design 2003.

17.  T.S. Rajesh Kumar, R. Govindarajan and C.P. Ravikumar.  Code and Data Layout for Embedded Systems. VLSI Design 2003.

18.  C.P. Ravikumar and T. Srinivas. Addressing the Power Concern in SoC Testing. VDAT 2002, Bangalore.

19.  C.P. Ravikumar, Janardan Mishra,  Nirmalya Haldar, Kamal Kiran, and Senthil Arasu. Static Verification of Burn-in Test Vectors. TI Test Symposium, 2002.

20.  C.P. Ravikumar. Techniques for Scan Test Power Optimization, TI Test Symposium, 2002.

21.  C.P. Ravikumar. Challenges in Testing of Deep-Submicron VLSI Circuits. Invited Talk presented at the Chandigraph Symposium on Microelectronics, organized by Indian Microelectronics Society. February 2002.

22.  Rahul Kumar and C.P. Ravikumar. Early Estimation of Leakage Power in an ASIC design flow". Presented at SNUG 2002, Bangalore.

23.  C.P. Ravikumar, Rahul Kumar.  Divide-and-Conquer IDDQ Testing for Core-based System Chips.  International Conference on VLSI Design. Bangalore, India, 2002. Pages 761-766.

24.  S. Chakraverty, C.P. Ravikumar, D.Roy Choudhuri. An Evolutionary Scheme for Cosynthesis of Real-Time Systems. International Conference on VLSI Design. Bangalore, India, 2002. Pages 251-256..

25.  M. M. Sufyan Beg, C. P. Ravikumar, "Measuring the Quality of Web Search Results", Proc. Sixth International Conference on Computer Science and Informatics - a track at the Sixth Joint Conference on Information Sciences (JCIS 2002), Durham, NC, USA, March 8-13, 2002, pp. 324-328.

26.  Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri.  Improvement of ASIC Design Processes. International Conference on VLSI Design. Bangalore, India, 2002. Pages 105-111.

27.  Rahul Kumar and C.P. Ravikumar. Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. International Conference on VLSI Design. Bangalore, India, 2002. Pages 45-50.

28.  Vineet Sahula and C.P. Ravikumar. The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes. International Conference on VLSI Design. Bangalore, India, 2001. Pages 91-96.

29.  V. Sankara Subramanian and C.P. Ravikumar. Estimating Crosstalk from VLSI Layouts. International Conference on VLSI Design. Bangalore, India, 2001. Pages 531-536. (Winner of Best Paper Award.)

30.  Vishal Dalal and C.P. Ravikumar. Software Power Optimizations in an Embedded System. Estimating Crosstalk from VLSI Layouts. International Conference on VLSI Design. Bangalore, India, 2001. Pages 254-259.

31.  Rajesh Kannah and C.P. Ravikumar. Functional Testing of Microprocessors with Graded Fault Coverage, Asian Test Symposium, Taiwan, November 2000.

32.  Sahula V., Ravikumar C.P. Design Planning for Single Chip Implementation of Digital Wireless Mobile Transceiver, ICPWC, 2000, Hyderabad, India.

33.  M.M.S. Beg and C.P. Ravikumar. Distributed Algorithms for Internet Resource Discovery. To be presented at ATC 2000, New Delhi, September 2000.

34.  Abhinav Mathur, C. P. Ravikumar. Advance Capacity Reservation for High Bandwidth Multimedia Traffic, National Conference on Communications, Kanpur, 2001.

35.  Anubhav Srivastava, C. P. Ravikumar, M. M. S. Beg. Enhanced Similarity Measure for Client – Directory - Server Model, National Conference on Communications, Kanpur, 2001, 42-46.

36.  C. P. Ravikumar, S. Chakraverty and D. RoywChowdhury, Synthesis of Performance Critical Heterogeneous ComputingSystems Using Genetic Algorithm under a Stochastic Framework. Presented at the National Conference on Intelligent Computing, Kalyani, West Bengal.

37.  M. M. Sufyan Beg and C. P. Ravikumar, "Distributed Resource Discovery from the Internet for e-Commerce Applications", 43rd Annual Technical Convention (ATC-2000) of IETE, New Delhi, September 30 - October 1, 2000.

38.  S.Chakraverty & C.P.Ravikumar. A Stochastic Framework for Co-synthesis of Real Time Systems. LCTES 2000, Vancouver, Canada. To appear in Lecture Notes, Springer Verlag, 2000.

  1. Anubhav Srivastava and C.P. Ravikumar. A New Distributed Resource Discovery Model. Proceedings of the National Seminar on Applied Systems Engineering and and Soft Computing, Agra, India, 2000, Pages 172-176.
  2. C.P. Ravikumar and D. Dhamija. An Evolutionary Algorithm for Optimisation of Shared WDM Networks. Proceedings of the National Seminar on Applied Systems Engineering and and Soft Computing, Agra, India, 2000, Pages 177-174.
  3. S. Chakraverty and C.P. Ravikumar. Genetic Algorithm for Synthesis of Performance-Critical Real-time Systems. Proceedings of the National Seminar on Applied Systems Engineering and and Soft Computing, Agra, India, 2000, Pages 281-288.
  4. Vineet Sahula and C.P. Ravikumar. Yield-oriented Design Planning for MCMs. EMIT 2000, Bangalore, February 2000.
  5. V. Shanbhogue and C.P. Ravikumar. Path Based Multicast Routing Algorithms for ATM Networks. Proceedings of National Conference on Communications, New Delhi, 2000. Pages 126-129.
  6. N.V. Balaji and C.P. Ravikumar. Improving the life of Mobile Ad-Hoc Networks through Energy-Conscious Routing. Proceedings of National Conference on Communications, New Delhi, 2000. Pages 332-335.
  7. S. Chakraverty and C.P. Ravikumar. Genetic Algorithm for Synthesis of Performance-critical Real-time Systems. To appear in Proceedings of the National Seminar on Applied Systems Engineering and Soft Computing, Agra, 2000.
  8. C.P. Ravikumar, A. Verma, G. Chandra. Power-constrained Test Scheduling in Core-based Systems. Proceedings of the 12th International Conference in VLSI Design, January, 2000, Calcutta.
  9. C.P. Ravikumar and S. Chopra. Interconnect testing in Core-based Systems. Proceedings of the 12th International Conference in VLSI Design, January, 2000, Calcutta.
  10. Sharma and C.P. Ravikumar. Efficient Implementation of ADPCM Codec. Proceedings of the 12th International Conference in VLSI Design, January, 2000, Calcutta.
  11. C.P. Ravikumar, M. Sharma, and P. Jain. Design of WDM Networks for Delay-bound Multicasting, Proceedings of International Conference on High-Performance Computing, December 1999, Calcutta.
  12. G. Kumar, N. Narang, and C.P. Ravikumar. Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications. Proceedings of International Conference on High-Performance Computing, December 1999, Calcutta.
  13. C.P. Ravikumar, G. Chandra, A. Verma. A Polynomial-time Algorithm for Power-Constrained Test Scheduling in Core-Based Systems. Proceedings of Asia Test Symposium, Hong Kong, 1999.
  14. Rohit Sharma and C.P. Ravikumar. Design issues in synthesis of reusable cores. Proceedings of the Great Lakes VLSI Symposium, Michigan, Ann Arbor, 1999. Pages 144-147.
  15. A Shyamprakash, Ram G. Mohan, C.P. Ravikumar. Parametrized Divided Cells for Synergy SmartBlocks. Proceedings of the Cadence Technical Conference, 1998. Pages 469-471.
  16. C.P. Ravikumar and N. Agrawal. Adaptive Routing in Multicomputers: A Tutorial. Presented at Workshop on High Performance Computing, Indian Statistical Institute, January 1999.
  17. C.P. Ravikumar, M. Sharma and R.K. Patney. Improving the Diagnosability of Digital Circuits. Proceedings of the 12th International Conference on VLSI Design (IEEE), Goa, 1999. Pages 629-634.
  18. C.P. Ravikumar and A. Mittal. Hierarchical Fault Delay Simulation. Proceedings of the 12th International Conference on VLSI Design (IEEE), Goa, 1999. Pages 635-639
  19. G. Kumar, N. Narang and C.P. Ravikumar. Efficient Algorithms for Delay-Bounded Minimum Cost Path Problem in Communication Networks. Proceedings of the 5th International Conference on High Performance Computing, Chennai, India, 1998. Pages 141-146.
  20. C.P. Ravikumar, D. Pandit and A. Mishra. Performance-driven Design and Redesign of High Speed Local Area Networks. Proceedings of the 5th International Conference on High Performance Computing, Chennai, India. Chennai, 1998, Pages 416-421.
  21. N. Agrawal and C.P. Ravikumar. Efficient algorithms for adaptive routing with deadlock-recovery.  Proceedings of  Europar-98, European conference on Parallel Processing, 1998.
  22. C.P. Ravikumar and N. Satyaprasad. Evaluating BIST Architectures for Low Power. Proceedings of 7th Asia Test Symposium (IEEE), 1998, Singapore. Pages 430-434.
  23. C.P.Ravikumar, Ram G.Mohan & S.Patel.  Delay constrained power minimisation through technology mapping and placement.  Proceedings on emerging microelectronics & interconnection technology. (EMIT '98). Pages 261--267.
  24. V.Sahula, C.P.Ravikumar & D.Nagchoudhari. Optimal interconnect modelling and synthesis.  Proceedings on emerging microelectronics & interconnection technology.(EMIT '98).
  25. C.P.Ravikumar J.Minocha & R.Aggarwal. MCM Partitioning for low power applications. Proceedings on emerging microelectronics & interconnection technology.(EMIT '98).
  26. S.A.Wadekar, A.C.Parker & C.P.Ravikumar. FREEDOM: Statistical behaviour estimation of system energy and power. Proc. of the 11th International conference on VLSI Design. Jan. 1998, Pages 30-36.
  27. C.P.Ravikumar,Sumit Gupta & Akshay Jajoo. Synthesis of testable RTL designs. Proceedings of the 11th International conference on VLSI Design. Jan. 1998, Pages 187-192. (Winner of Best Student Paper Award).
  28. M.F.Abdulla, C.P.Ravikumar & Anshul Kumar.  Hybrid testing schemes based on mutual and signature testing.  Proceedings of the 11th International conference on VLSI Design. Jan. 1998, Pages 293-296.
  29. Dong-Hyun Heo, A.C.Parker, C.P. Ravikumar.  An evolutionary approach to system redesign. Proceedings of the 11th International conference on VLSI Design. Jan. 1998, Pages 359-362.
  30. D.R.Pandit & C.P.Ravikumar. Call admission control and routing in ATM networks for multimedia communications. Proceedings of the international conference on multimedia, Jan 1998, Pages 94-102
  31. M.F. Abdulla, C.P. Ravikumar & Anshul Kumar. On-chip signature checking for embedded memories. Proceedings of the 11th International conference on VLSI Design, Chennai, India. Jan. 1998, Pages 558-563.
  32. Ramnik Bajaj, C.P. Ravikumar & Suresh Chandra.  Distributed delay constrained multicast path setup algorithm for high speed networks. Proceedings on Fourth international conference on High Performance computing. Dec.1997, Pages 438-442
  33. C.P. Ravikumar, Varun Varma and Tarun Rai. Kautz Graph Logical Topology with Adaptive Routing for Multihop Lightwave Networks. Indian Conference on Computer Communications, Calcutta, India, 1997.
  34. C.P. Ravikumar, A.R. Thomas and A. Gupta. A Genetic Algorithm for Assembling Optical Computers Using Faulty Optical Arrays, International Conference on High-Performance Computing, December 1996, India.
  35. S. Habib, C.P. Ravikumar and A.C. Parker.  Storage Allocation and Scheduling Problems in Web Caching Applications.  International Workshop on Web Caching, organized by NLANR, USA.  Colorado, Boulder.  USA. 1997.
  36. Dong-Hyun Heo & A.C.Parker, C.P. Ravikumar. Rapid synthesis of multichip systems.  Proceedings of the 10th International conference on VLSI Design. Jan. 1997, Pages62-68.
  37. C.P. Ravikumar & R. Aggarwal. A graph-theoretic approach for register file based synthesis.  Proceedings of the 10th International conference on VLSI Design. Jan. 1997, Pages 118-123.
  38. M.F. Abdulla, C.P.Ravikumar & Anshul Kumar. Efficient implementation of multiple on-chip signature checking. Proceedings of the 10th International conference on VLSI Design. Jan. 1997, Pages 297-302.
  39. M.F. Abdulla, C.P. Ravikumar & Anshul Kumar. A Scheme for Multiple On-chip Signature Checking for Embedded SRAMs. Proceedings of IEEE European Design and Test Conference, Paris, France, 1997.
  40. Anubhav Mishra & C.P.Ravikumar. Design and performance analysis of a cellular network with support for multicasting.  Proc. of the international conference on multimedia, Jan 1998, Pages103-113.
  41. Dong-Hyun Heo & A.C.Parker,C.P.Ravikumar. Synthesis of optimal MCM-based systems. EEP-vol. 19-1, Advances in electronic packaging-1997,Vol.1, ACME 1997,  Pages 843-850
  42. C.P.Ravikumar,Vikas Jain & Anurag Dod. Faster fault simulation through distributed computing. Proceedings of the 10th International conference on VLSI Design. Jan. 1997, Pages482-487.
  43. N. Agrawal & C.P.Ravikumar. An Euler-tour based technique for deadlock-free multicasting. Proc. of international conference on parallel processing. August 1997,Chicago,IL. Pages 378--384.
  44. C.P.Ravikumar & V.Arora. Deadlock-free multicasting in multicomputers based on Two-path Cover. Proceedings of  ADCOMP '97, Chennai, INDIA,1997. Pages 493--500.
  45. C.P. Ravikumar & C.P.Gupta. Parallel algorithm for branch-and-bound. Proceedings of international conference advanced computing (ADCOMP '97), Chennai, and India.  Pages 431--438.
  46. C.P. Ravikumar, Dilip Raj Pandit, Anubhav Mishra & Abhinav Mathur. Topological design of Local Area Networks. Southeast asia region conference on communications,New Delhi 1997.
  47. D.-H. Heo, C.P. Ravikumar and A.C. Parker.  A Synthesis tool targeted for Rapid Delivery of Electronic Systems.  International Workshop on Electronic Design Processes (IEEE), Santa Clara, April 1996.
  48. C.P. Ravikumar, N. Agrawal and P. Agarwal.  Efficient Delay Test Generation for Module-level Circuits.  In Proceedings of the Great Lakes VLSI Symposium (IEEE), 1996.
  49. C.P. Ravikumar, S. Ahmad and V. Agrawal.  Path Cover Problem for General Graphs with applications to Deadlock-free routing in multicomputers.  Computer Society of India's Annual Convention, Bangalore, India, October 1996. Pages 271-277.
  50. N. Sharma and C.P. Ravikumar.  Improving the confidence of IDDQ testing through Testability-driven Layout.  International Symposium on IDDQ Testing, 1996.
  51. N. Agrawal and C.P. Ravikumar. Adaptive Multicasting in Massively Parallel Computers. December, 1996. Proceedings of the International Conference on Advanced Computing (ADCOMP '96). Bangalore, India. Pages 151-160.
  52. M.F. Abdulla,C.P. Ravikumar, and A. Kumar. A novel test architecture with built-in self check. Proceedings of the VLSI Design Conference, Bangalore, India, 1996. Pages 57-60.
  53. M.F. Abdulla, C.P. Ravikumar, and A. Kumar. BIST with Multiple On-chip Signature Comparisons. IEEE European Test Workshop, Montpellier, France, Pages 27-31, 1996.
  54. C.P. Ravikumar and V.Sexena. Synthesis of Testable Pipelined Datapaths using Genetic Search.Preceedings of VLSI Design 96,  Bangalore India 1996.
  55. C.P. Ravikumar and R.Rajarajan. Genetic Algorithms for Scan design Problems. Proceedings of VLSIdesign 96,Banglore India 1996.
  56. C.P.Ravikumar, M.R.Prasad and L.S. Hora. Estimation of Power from Module-level Netlists. Proceedings of VLSI Design  96, Banglore India 1996.
  57. N. Agrawal and C.P. Ravikumar. Randomized Adaptive Routing for Massively Parallel Computers. Proceedings of the First Conference on Fault-tolerant Systems, 1995, Madras, India. Pages 165-171.
  58. C.P. Ravikumar and G. Manimaran. Multistage Indirect-star interconnection network for ATM Switch Architecture. Proceedings of the First Conference on Fault-tolerant Systems, 1995, Madras, India.
  59. R. Parthiban, C.P. Ravikumar, R. Kakarala, and J. Sivaswamy.  Parallel algorithms for symmetry detection. In Proc. of Int. Conference on High Performance Computing, pages 569--573, 1995.
  60. N. Agrawal and C.P. Ravikumar.  Hierarchical Routing Algorithm for Multiply Twisted Hypercubes. In Proceedings of Parallel and Real-time Systems Conference   (PART), Australia, 1995.
  61. Shyamprakash and C.P. Ravikumar. Verilog Modeling and Simulation of a Communication Coprocessor for  Multicomputers. In Open Verilog Interface Conference, Santa Barbara (IEEE), 1995.
  62. C.P. Ravikumar, V.Jain, and G.S. Thandi. Simulated Annealing for Technology Mapping in FPGAs.  In Proceedings of National Systems Conference, Agra, India, Pages 400--405, January 1995.
  63. C.P. Ravikumar and H.Joshi. HISCOAP -- A Hierarchical Testability Analysis Tool. In Proc. of the International Conference of VLSI Design  (IEEE), New Delhi, India, Pages 272--277, January 1995.
  64. C.P. Ravikumar. A Redundant Arithmetic CORDIC Chip. Proceedings of SPCOM-95,National Meeting of Signal processing and Communication, Banglore ,India.August 1995.
  65. C.P. Ravikumar and R.Aggarwal. A Parallel Search-and-Learn Algorithm for Graph Coloring. In Proceedings of the International Workshop on Parallel Processing, Bangalore, India}, Pages 61--66, December 1994.
  66. C.P. Ravikumar and G.Manimaran. An ATM Switch Fabric Based on Indirect Star Graphs. In Symposium on Parallel and Distributed Processing (IEEE), Dallas, 1994.
  67. C.P. Ravikumar and A.Shyamprakash. VLSI Implementation of a Wormhole Router using Virtual Channels. In Proceedings of the IEEE Tencon, Singapore, Pages 1035--1039, 1994.
  68. C.P. Ravikumar and A.M. Goel. Deadlock Free Routing Algorithms for Star Graphs. In Proceedings of the National Symposium on Theoretical Computer Science, Kanpur, India, June 1994.
  69. C.P. Ravikumar and H. Rasheed. Simulated Annealing for Target-Oriented Partial Scan.  In the Proceedings of the International Conference on VLSI Design (IEEE), Calcutta, India, January 1994. Pages 107 -- 112.
  70. C.P. Ravikumar and A. Kuchlous.  Two-way Partitioning of Shuffle-Exchange and DeBruijn Graphs.  In the Proceedings of the National Symposium on Theoretical Computer Science, Kharagpur, India.  June 1993. Pages 1--10.
  71. C.P. Ravikumar, A. Kuchlous, and G. Manimaran.  Incomplete Star Graph -- An Economical, Fault-tolerant Interconnection Network.  In the Proceedings of the International Conference on Parallel Processing, St. Charles, Illinois, USA. August 1993. Pages I-83 -- I-90.
  72. C.P. Ravikumar. Parallel Search-and-Learn Technique for Solving Large Scale TSP. In the Proceedings of the International Conference on Tools with Artificial Intelligence (IEEE), Boston, USA. 1993. 381 -- 388.
  73. C.P. Ravikumar and R.K. Gandhi. Parallel Neural Algorithm for Solving Large Scale TSP.  In the Proceedings of the National Systems Conference, Kanpur, India, December 1993. Pages 122--126.
  74. C.P. Ravikumar, R.K. Gandhi and L.M. Patnaik. Parallel Neural Algorithm for TSP Based on Divide-and-Conquer, ANZIIS Conference (IEEE), December 1993, Australia.
  75. C.P. Ravikumar and R. Sethi.  SHARP -- A Parallel Shape Recognition Algorithm.  In the Proceedings of the Indo-US Workshop on Parallel Algorithms for Digital Signal Processing, Pune (India), 1993.
  76. C.P. Ravikumar. Solving Physical Design Problems on a Vector Machine. International Conference on VLSI Design 1992. Pages 109-116.
  77. C.P. Ravikumar and S. Sastry, "Parallel Algorithms for Coloring Perfect Graphs with Applications to VLSI Layout and Synthesis," in Proc. 4th Annual Parallel Processing Symp., pp. 587-596, Apr. 1990.
  78. C.P. Ravikukmar and S. Sastry, "A Parallel Algorithm for Coloring Interval Graphs with Applications to Gate Matrix Layout and Register Allocation," in Proc. Int'l Conf. on VLSI, (Bangalore, India), pp. 189- 192, Dec. 1989.
  79. C. P. Ravikumar and S. Sastry, "A Parallel Approach to Three Layer Channel Routing," in Proc. Int'l Workshop on Hardware Accelerators for CAD, (Oxford University, U.K.), pp. 259-272, Sept. 1989.
  80. C.P. Ravikumar and S. Sastry, "LARA : A Layout Accelerator Based on Reduced Array Architecture," in Proc. Int'l Workshop on Hardware Accelerators for CAD, (University of Oxford, U.K.), pp. 233-244, Sept 1989.
  81. C.P. Ravikumar and S. Sastry, "Parallel Placement on Hypercube Architecture," in Proc. Int'l Conf. on Parallel Processing, pp. 97-101, 1989.
  82. C.P. Ravikumar, S. Sastry, and L. Patnaik, "A Data Parallel Approach to Local Search Placement Algorithms," in Proc. Int'l Conf. on VLSI, (Bangalore, India), pp. 13-20, Dec. 1988.
  83. C.P. Ravikumar, and S. Sastry, "Parallel Placement on Reduced Array Architecture," in IEEE Design Automation Conf. (DAC), pp. 121-127, June 1988.
  84. C.P. RaviKumar, L.M. Patnaik, Parallel Placement by Simulated Annealing, Proceedings of 1987 IEEE international Conference on Computer Design, pp. 91-94
  85. C. P. Ravikumar, Lalit M. Patnaik: An Architecture for CSP and Its Simulation. ICPP 1987: 874-881

[1] This paper was awarded the “Best Paper Award” at the 14th International Conference on VLSI Design, Bangalore, January 3-7, 2001.